Navigation

BA/MA – Control and Communication Module for MMC Subcell

Control and Communication Module for a Modular Multilevel Converter (MMC) Subcell

The modular multilevel converter (MMC) has become the preferred topology for HVDC transmission and comes into focus for many lower-power applications (e.g. industrial drives, wind power). One challenge is the highly complex communication system, consisting of hundreds of fiber-optic links. The industrial fieldbus EtherCAT has been proposed to replace the individual fiber-optic links, but suffers from high cycle times. To some extent the cycle times are self-made by using non-optimal components and interfaces.

In this thesis you will design and test a control & communication module with focus on low latencies. In contrast to existing research you will replace the Ethernet PHY with LVDS transceivers, which have very low propagation delay. The interface between microcontroller and EtherCAT communication ASIC shall be based on the external memory interface (EMIF), which is normally used for SRAM memory chips. A speed-up is expected in comparison to the conventionally used SPI.

Your key-care-about is:

  • PCB design and test around microcontroller and communication ASIC
  • Adaption of existing code for the EMIF communication

Prerequisites:

  • Background in power electronics or signal processing
  • Experience in PCB design and test
  • C programming skills

The thesis can be done in English or German.

Betreuer: Martin Angerer

Für Studienfächer: EEI

Frühest möglicher Beginn: Sofort

Verantwortlicher: Prof. Dr.-Ing. Martin März